Sudhakar M. Reddy

Joined the College of Engineering: 1966 

Education: Ph.D., Electrical Engineering, University of Iowa, 1968
M.E., Electrical Engineering, Indian Institute of Science, 1963
B.E., Electrical Engineering, Osmania University, 1962
B.Sc., Physics, Osmania University, 1958

Special Fields of Knowledge: VLSI circuit design and test; Coding/Theory; digital systems reliability; computer communications.

Present Research Interests: CAD for VLSI Circuits; VLSI Circuit Testing and design for testability.

Selected Publications: 

• Rajski, J., Tyszer, J., Wang, C., Reddy, S.M., "Finite memory test response compactors for embedded test applications," IEEE Transactions on Computer-Aided Design, 622-634, April 2005.
• Devtaprasanna, N., Gunda, A., Krishnamurthy, P., Reddy, S.M., and Pomeranz, I., "Methods for improving transition delay fault coverage using broadside tests," IEEE International Test Conference, November 2005, pp. 256-265. 
• Zhang, Z., Reddy, S.M., Pomeranz, I., Lin, X., and Rajski, J., "Scan tests with multiple fault activation cycles for delay faults," Proc. VLSI Test Symposium 2006.
• Chen, G., Reddy, S.M., Pomeranz, I., and Rajski, J., "A test pattern ordering algorithm for diagnosis with truncated fail data," Proc. Design Automation Conference 2006, pp. 399-404.
• Pomeranz, I. and Reddy, S.M., "Generation of functional broadside tests for transition faults," IEEE Transactions of Computer-Aided Design, 2207-2218, October 2006.

Active Scientific and Professional Society Memberships: Institute of Electrical and Electronics Engineering Computer Society; Information Theory Group; Circuits and Systems Society; Communications Society; Life Fellow, Institute of Electrical Electronics Engineers.