55:035 - Computer Architecture and Organization

Spring 2009

Using the ModelSim Verilog Environment

This page will give you a quick help to set up your CSS HP-Unix enviroinment to work with the ModelSim Verilog tools that are a part of the Mentor Graphics tool suite..

The tool used is named ModelSim6.4 and it works with either VHDL or Verilog code.

Using Verilog will be very similar to classical programming languages (such as C). You will perform the following steps:

  • Write your Verilogcode using any text editor (a usual convention gives the extension .v to Verilog source files), for example my_test.v.
  • Compile your my_test.v file using the ModelSim compiler to check if the syntax is correct (if not, some debugging messages will appear to help you change your code and get it to compile properly).
  • Run the ModelSim simulation tool which will allow you to exercise your compiled code and look at its behavior, timing characteristics, etc.

Before starting to write Verilog code you need to do a few easy operations:

  • Make sure you are using bash as your shell (it should be your default shell).
  • Go to your home directory
    $ cd
  • First, you have to source the Mentor setup file by typing the line below at your prompt:
    $ . /usr/css/etc/mentor_setup.sh
    (Note: there is a space between the dot and the slash)

To avoid having to source this file every time you start a session on your workstation, you can add the source command line in your .bashrc file (which is in your home directory):

  • Open your .bashrc file with a text editor.
    (i.e. $ pico .bashrc)
  • Add the folowing two lines at the end of the file (the first line is only a comment):
    # Source of setup file for Mentor Tools
    source /usr/css/etc/mentor_setup.sh
    Make sure you type the file's path correctly!
  • Now, in the future, when you start a session you will not need to type the source command.

Important note: if you do not want to add this information to your .bashrc file, you have to type the source command everytime you start a session!

  • Next, you will create a directory that will contain all your Verilog files, simulation results, etc. (you do not have to create this directory, but it will help organize your work). Type:
    $ mkdir verilog_dir
  • Then go to that directory by typing:
    $ cd verilog_dir
  • Now we have to create the working library. This step creates a sub-directory contained in the verilog_dir directory:
    $ vlib work

You can now write Verilog modules using a text editor. Once you have saved a Verilog file (e.g. my_test.v) into your verilog_dir directory, you should do the following steps, with verilog_dir as your working directory:

  • Compile your file by typing:
    $ vlog my_test.v
    If the compilation is successful, you will have a result that will look similar to this:
    Model Technology ModelSim SE vlog 6.1b Compiler 2005.09 Sep 8 2005
    -- Compiling module your_module_name
    ...
    Top level modules: your_top_level_module_name(s)

If compilation failed, apropriate error messages will be displayed. You will not be able to simulate a Verilog code that has not been compiled successfully. Also remember that even if you know you have a syntaxically correct code, you must compile it before running it.

  • If your my_test.v file was compiled successfully you can simulate it by typing:
    $ vsim top_level_module_name
    Note: When running a simulation, you must specify the top-level module name, not the file name.
    This will run the ModelSim simulator and a window will pop up.
  • You can now open additional windows that you wish to view by choosing an option under the View pull-down menu in the ModelSim SE PLUS 6.1b window, for instance View -> Signals... and View -> Waves.... for now you will not need any additional windows, but you may want to play around with the options to familiarize yourself with the capabilities and features of ModelSim.
  • You are now ready to Run the program. You can use the "run" menu items or run icons in the ModelSim window to run the simulation for specified numbers of timesteps. Output from display and monitor statements will be displayed in the ModelSim window.
  • Note: If you are working from a text-only shell (e.g. a telnet or SSH connection) you can run vsim in a non-graphical mode by specifying the -c flag:
    $ vsim -c top_level_module_name
  • In this case, you will get a command prompt of the form
    VSIM>
  • You can run the simulation for a specified number of timesteps byu typing the run command at this prompt. For instance to run for 100 time steps, type:
    VSIM> run 100
  • You can run the simulation until it is terminating by using the -all option; this is also useful to obtain the file transcript for the complete execution:
    VSIM> run -all
  • Use CTRL-D to leave the command-line mode of ModelSim

You now have the basics needed to write, compile and run/simulate a Verilog application. . You are encouraged to try the tool yourself since it is probably the most efficient way for you to get familiar to it.

FOR MORE INFORMATION ABOUT MODELSIM, look at the Help at the window.

Last Updated: DCM