55:035 Spring 2009
Computer Architecture and Organization
General Information:
The project consists of three main components:
·
SISC processor, built in synthesizable VerilogHDL,
along with: (70% of total)
1. A Test Bench for the SISC
processor, built in VerilogHDL
2. A program which
demonstrates proper execution of each instruction type (using the test bench
and Modelsim)
·
These 5 hand-assembled programs which execute on the SISC processor: (30%
of total)
1. The first 10 numbers in
the Fibonacci sequence, storing the results in memory
2. Sort list of 10 signed
integers in memory
3. Add a list of 5 signed
integers in memory, storing the result in memory
4. Multiply two positive
numbers from memory, storing the result in memory
5. Divide two positive
numbers from memory, storing the result in memory
Overview of the SISC Architecture:
What to Turn In:
Turn in the following to the ICON project dropbox
by midnight, April 17th:
1. VerilogHDL for the SISC processor
2. VerilogHDL for the testbench
3. Machine code (as text file)
for the first program (each instruction)
4. “do” files for shell
scripts that would aid in compiling and running your design in the simulator
Turn in the
following to the ICON project dropbox by midnight,
May 1st:
1. Updated Verilog
for the SISC processor or test bench (if you have any updates)
2. Machine code (as text files)
for the other 5 each of the hand-assembled programs
3. “do” files for
shell scripts that would aid in compiling and running your design in the
simulator
Grading:
First
Submittal:
1.
Correctly compile in Modelsim
15%
2.
Correctly load in Modelsim
15%
3.
Proper execution of each instruction: 14
instructions at 5% each
Second Submittal:
1.
Proper execution of each of the 5 programs: 20% each
Last Update: April 22, 2009 DCM